raimon@argo
f111aa1c79
- [FIX] opcodes accesibles - [NEW] El desensamblador ja no mostra parts del mapa de memòria que no son RAM o ROM - [FIX] Ja se mostren gràficament tots els branch - [NEW] memdebuginfo de tots els dispositius mapejats disponible
139 lines
4.1 KiB
C++
139 lines
4.1 KiB
C++
#include "pia.h"
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namespace pia
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{
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uint8_t ram[128];
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bool timer_interrupt = false;
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uint8_t timer_value = 0;
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uint16_t prescaler = 0;
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uint16_t divider = 0;
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bool timer_underflow = false;
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void reset()
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{
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}
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void tick()
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{
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prescaler++;
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if (!timer_underflow) {
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if (prescaler >= divider) {
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prescaler = 0;
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if (timer_value == 0) {
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timer_underflow = true;
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timer_interrupt = true;
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timer_value = 0xff;
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} else {
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timer_value--;
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}
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}
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} else {
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timer_value--;
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}
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}
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uint8_t read(uint16_t address)
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{
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if (address & 0x200) {
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if ( (address & 0x04) ) {
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// Timer functions
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if (address & 0x01) {
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uint8_t flags = timer_interrupt ? 0x80 : 0x00;
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timer_interrupt = false;
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return flags;
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} else {
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return timer_value;
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}
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} else {
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// I/O Ports
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switch( address & 0x03) {
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case 0x00: // [TODO] SWCHA
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return 0xff;
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case 0x01: // [TODO] DDRA
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return 0x00;
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case 0x02: // [TODO] SWCHB
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return 0x03;
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case 0x03: // [TODO] DDRB
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return 0x00;
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default:
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return 0x00;
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}
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}
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} else {
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return ram[address & 0x7f];
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}
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}
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void write(uint16_t address, uint8_t value)
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{
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if (address & 0x200) {
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if ( (address & 0x04) ) {
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if ( (address & 0x10) ) {
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// Timer functions
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switch( address & 0x03) {
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case 0x00: // [TODO] TIM1T
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divider = 1;
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timer_value = value;
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prescaler = 0;
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timer_underflow = false;
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timer_interrupt = false;
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break;
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case 0x01: // [TODO] TIM8T
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divider = 8;
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timer_value = value;
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prescaler = 0;
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timer_underflow = false;
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timer_interrupt = false;
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break;
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case 0x02: // [TODO] TIM64T
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divider = 64;
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timer_value = value;
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prescaler = 0;
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timer_underflow = false;
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timer_interrupt = false;
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break;
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case 0x03: // [TODO] TIM1024T
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divider = 1024;
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timer_value = value;
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prescaler = 0;
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timer_underflow = false;
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timer_interrupt = false;
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break;
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}
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} else {
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// Funcionalitat relacionada amb les interrupcions. Ignorar per a la Atari 2600
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}
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} else {
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// I/O Ports
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switch( address & 0x03) {
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case 0x00: // [TODO] SWCHA
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break;
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case 0x01: // [TODO] DDRA
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break;
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case 0x02: // [TODO] SWCHB
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break;
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case 0x03: // [TODO] DDRB
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break;
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}
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}
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} else {
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ram[address & 0x7f] = value;
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}
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}
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namespace debug
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{
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const memDebugInfo getInfo(uint16_t address)
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{
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if (address & 0x200) {
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return {"PIA", mdtRegister, address};
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} else {
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return {"RAM", mdtRAM, address & 0xff};
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}
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}
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}
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}
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