- [NEW] Mode +2A/+3 funcionant, a falta de la unitat de disc

This commit is contained in:
2025-08-05 08:24:45 +02:00
parent 9eb8662ec7
commit ade97a9a70
5 changed files with 110 additions and 4 deletions

View File

@@ -8,6 +8,10 @@
#define ZX_128MEM_ROM 0x10
#define ZX_128MEM_DISPAG 0x20
#define ZX_2A_3_PAGING_MODE 0x01
#define ZX_2A_3_HROM 0x04
#define ZX_2A_3_SPECIAL 0x06
namespace mem
{
uint8_t mode = ZX_48K;
@@ -18,9 +22,11 @@ namespace mem
uint8_t *slot[8];
bool writable[8];
uint8_t config_128K;
uint8_t config_128K = 0;
uint8_t config_2A_3 = 0;
void zx_128_port_out(int port, int val);
void zx_2A_3_port_out(int port, int val);
void init(uint8_t mode)
{
@@ -77,6 +83,28 @@ namespace mem
z80::connect_port(0x7ffd, 0x8002, nullptr, mem::zx_128_port_out);
break;
case ZX_PLUS3:
ram_size = 128*1024;
ram = (uint8_t*)malloc(ram_size);
for (int i=0x0000; i<ram_size; ++i) ram[i] = 0;
rom_size = 64*1024;
rom = (uint8_t*)malloc(rom_size);
f = fopen("plus3.rom", "rb");
fread(rom, rom_size, 1, f);
fclose(f);
slot[0] = &rom[0*8192]; slot[1] = &rom[1*8192];
slot[2] = &ram[10*8192]; slot[3] = &ram[11*8192];
slot[4] = &ram[4*8192]; slot[5] = &ram[5*8192];
slot[6] = &ram[0*8192]; slot[7] = &ram[1*8192];
writable[0] = writable[1] = false;
for (int i=2;i<8;++i) writable[i] = true;
z80::connect_port(0x7ffd, 0xc002, nullptr, mem::zx_128_port_out);
z80::connect_port(0x1ffd, 0xf002, nullptr, mem::zx_2A_3_port_out);
break;
}
}
@@ -143,19 +171,70 @@ namespace mem
const bool shadow = config_128K & ZX_128MEM_SCREEN;
config_128K = val;
if (config_2A_3 & ZX_2A_3_PAGING_MODE) return;
if (config_128K & ZX_128MEM_SCREEN) {
if (!shadow) zxscreen::setBaseAddresses(0x4000*7, 0x1800+0x4000*7);
} else {
if (shadow) zxscreen::setBaseAddresses(0x4000*5, 0x1800+0x4000*5);
}
uint8_t hrom = (config_2A_3 & ZX_2A_3_HROM) ? 4 : 0;
if (config_128K & ZX_128MEM_ROM) {
slot[0] = &rom[2*8192]; slot[1] = &rom[3*8192];
slot[0] = &rom[(hrom+2)*8192]; slot[1] = &rom[(hrom+3)*8192];
} else {
slot[0] = &rom[0*8192]; slot[1] = &rom[1*8192];
slot[0] = &rom[(hrom+0)*8192]; slot[1] = &rom[(hrom+1)*8192];
}
const uint8_t slot3 = (config_128K&ZX_128MEM_PAGE)*2;
slot[6] = &ram[slot3*8192]; slot[7] = &ram[(slot3+1)*8192];
}
void zx_2A_3_port_out(int port, int val)
{
if (port != 0x1ffd) return;
if (config_128K & ZX_128MEM_DISPAG) return;
config_2A_3 = val;
if (config_2A_3 & ZX_2A_3_PAGING_MODE) {
for (int i=0;i<8;++i) writable[i] = true;
switch ((config_2A_3 & ZX_2A_3_SPECIAL)>>1)
{
case 0:
slot[0] = &ram[0*8192]; slot[1] = &ram[1*8192];
slot[2] = &ram[2*8192]; slot[3] = &ram[3*8192];
slot[4] = &ram[4*8192]; slot[5] = &ram[5*8192];
slot[6] = &ram[6*8192]; slot[7] = &ram[7*8192];
break;
case 1:
slot[0] = &ram[8*8192]; slot[1] = &ram[9*8192];
slot[2] = &ram[10*8192]; slot[3] = &ram[11*8192];
slot[4] = &ram[12*8192]; slot[5] = &ram[13*8192];
slot[6] = &ram[14*8192]; slot[7] = &ram[15*8192];
break;
case 2:
slot[0] = &ram[8*8192]; slot[1] = &ram[9*8192];
slot[2] = &ram[10*8192]; slot[3] = &ram[11*8192];
slot[4] = &ram[12*8192]; slot[5] = &ram[13*8192];
slot[6] = &ram[6*8192]; slot[7] = &ram[7*8192];
break;
case 3:
slot[0] = &ram[8*8192]; slot[1] = &ram[9*8192];
slot[2] = &ram[14*8192]; slot[3] = &ram[15*8192];
slot[4] = &ram[12*8192]; slot[5] = &ram[13*8192];
slot[6] = &ram[6*8192]; slot[7] = &ram[7*8192];
break;
}
} else {
writable[0] = writable[1] = false;
for (int i=2;i<8;++i) writable[i] = true;
uint8_t hrom = (config_2A_3 & ZX_2A_3_HROM) ? 4 : 0;
if (config_128K & ZX_128MEM_ROM) {
slot[0] = &rom[(hrom+2)*8192]; slot[1] = &rom[(hrom+3)*8192];
} else {
slot[0] = &rom[(hrom+0)*8192]; slot[1] = &rom[(hrom+1)*8192];
}
}
}
}