- [NEW] Simbols de sistema de la Atari 2600 inclosos
- [FIX] opcodes accesibles - [NEW] El desensamblador ja no mostra parts del mapa de memòria que no son RAM o ROM - [FIX] Ja se mostren gràficament tots els branch - [NEW] memdebuginfo de tots els dispositius mapejats disponible
This commit is contained in:
raimon@argo
@@ -3,6 +3,8 @@
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namespace m6502
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{
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namespace opcodes
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{
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enum instruction {
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iADC, iAND, iASL, iBCC, iBCS, iBEQ, iBIT, iBMI, iBNE, iBPL, iBRK, iBVC, iBVS, iCLC,
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iCLD, iCLI, iCLV, iCMP, iCPX, iCPY, iDEC, iDEX, iDEY, iEOR, iINC, iINX, iINY, iJMP,
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@@ -23,7 +25,7 @@ namespace m6502
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const char *description;
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};
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const instructionProperties instructions[] = {
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inline const instructionProperties instructions[] = {
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{"ADC", fgArithmetic, "Add with Carry", "", "This instruction adds the contents of a memory location to the accumulator together with the carry bit. If overflow occurs the carry bit is set, this enables multiple byte addition to be performed." },
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{"AND", fgLogical, "Logical AND", "", "A logical AND is performed, bit by bit, on the accumulator contents using the contents of a byte of memory." },
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{"ASL", fgShift, "Arithmetic Shift Left", "", "This operation shifts all the bits of the accumulator or memory contents one bit left. Bit 0 is set to 0 and bit 7 is placed in the carry flag. The effect of this operation is to multiply the memory contents by 2 (ignoring 2's complement considerations), setting the carry if the result will not fit in 8 bits." },
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@@ -95,7 +97,7 @@ namespace m6502
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const char *postText;
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};
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const addressingModeProperties addressingModes[] = {
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inline const addressingModeProperties addressingModes[] = {
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{"Implicit", 1, "", ""},
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{"Accumulator", 1, "A", ""},
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{"Immediate", 2, "#", ""},
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@@ -119,7 +121,7 @@ namespace m6502
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bool ifBranchTaken;
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};
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const opcodeProperties opcodeDescriptors[256] = {
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inline const opcodeProperties opcodeDescriptors[256] = {
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{iBRK, amImplicit, 7, false, false},
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{iORA, amIndirectX, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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@@ -377,4 +379,6 @@ namespace m6502
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{iINC, amAbsoluteX, 7, false, false},
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{iILL, amImplicit, 2, false, false},
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};
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}
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}
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+24
-4
@@ -5,6 +5,7 @@
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#include "mem.h"
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#include "6502m.h"
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#include "6502dis.h"
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#include "6502_opcodes.h"
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#include "display.h"
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#include "ui.h"
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#include "ui_window.h"
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@@ -435,6 +436,8 @@ namespace m6502debugger
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void printDissasemblerLine(const uint16_t address, const int line, const bool heuristics=false)
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{
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const bool isMemory = mem::debug::getInfo(address).memType & mdtMemory;
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uint8_t colors[4] = { COLOR_RED, COLOR_CYAN, COLOR_WHITE, COLOR_WHITE};
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const uint8_t tag = tags[address];
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if ( !(tag & (MEMTAG_TINST | MEMTAG_TREPEAT)) ) colors[3]=COLOR_GRAY;
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@@ -448,6 +451,8 @@ namespace m6502debugger
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if (breakpoints[address]&9) ui::printtxt(0,line,"*", colors[0]);
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ui::printtxt(1,line,tohex(address,4), colors[1]);
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if (!isMemory) return;
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if ( (tag & MEMTAG_INST) || heuristics ) {
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const char *sym = m6502dis::getSymbol(address);
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if (sym[0]!=0) ui::printtxt(7,line, sym, COLOR_YELLOW);
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@@ -493,20 +498,21 @@ namespace m6502debugger
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printDissasemblerLine(pc, (num_lines/2)-1, true);
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for (int i=num_lines/2;i<num_lines;++i) {
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pos += m6502dis::getOpcodeSize(pos);
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pos += mem::debug::getInfo(pos).memType&mdtMemory ? m6502dis::getOpcodeSize(pos) : 1;
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line_address[i] = pos;
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printDissasemblerLine(pos, i, true);
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}
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pos = pc;
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for (int i=(num_lines/2)-2;i>=0;--i) {
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pos = find_previous_opcode(pos);
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pos = mem::debug::getInfo(pos).memType&mdtMemory ? find_previous_opcode(pos) : 1;
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line_address[i] = pos;
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printDissasemblerLine(pos, i, true);
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}
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for (int i=0;i<num_lines;++i) {
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if (mem::read(line_address[i])==0xd0) {
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if (m6502::opcodes::instructions[m6502::opcodes::opcodeDescriptors[mem::read(line_address[i])].instr].group == m6502::opcodes::fgBranch) {
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// if (mem::read(line_address[i])==0xd0) {
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int8_t offset = mem::read(line_address[i]+1);
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uint16_t target_address = line_address[i] + 2 + offset;
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if (offset<0) {
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@@ -526,7 +532,21 @@ namespace m6502debugger
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ui::printvline(17,i,-1,COLOR_RED);
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}
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} else {
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int j = i;
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while (j<num_lines){
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if (line_address[j] == target_address) {
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ui::printhline(17,i,18,COLOR_RED);
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ui::printhline(17,j,18,COLOR_RED);
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ui::printvline(17,i,j,COLOR_RED);
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break;
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}
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j++;
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}
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if (j==num_lines) {
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ui::printhline(17,i,18,COLOR_RED);
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//ui::printhline(17,0,18,COLOR_RED);
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ui::printvline(17,i,num_lines,COLOR_RED);
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}
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}
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//ui::printtxt(6,i,tohex(target_address,4),COLOR_BLACK);
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}
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@@ -1,6 +1,15 @@
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#pragma once
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#include <stdint.h>
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enum mappedDeviceType {
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mdtMemory = 1,
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mdtRead = 2,
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mdtWrite = 4,
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mdtROM = 3,
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mdtRAM = 7,
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mdtRegister = 8
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};
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struct memDebugInfo {
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const char* name;
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uint8_t memType;
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+5
-1
@@ -127,7 +127,11 @@ namespace pia
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{
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const memDebugInfo getInfo(uint16_t address)
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{
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if (address & 0x200) {
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return {"PIA", mdtRegister, address};
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} else {
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return {"RAM", mdtRAM, address & 0xff};
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}
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}
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}
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@@ -37,4 +37,11 @@ namespace rom
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data[address & mask] = value;
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}
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namespace debug
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{
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const memDebugInfo getInfo(uint16_t address)
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{
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return {"ROM", mdtROM, 0x1000 | (address & mask)};
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}
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}
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}
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@@ -461,4 +461,12 @@ namespace tia
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return rdy_low;
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}
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namespace debug
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{
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const memDebugInfo getInfo(uint16_t address)
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{
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return {"TIA", mdtRegister, address};
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}
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}
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}
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+72
-1
@@ -1 +1,72 @@
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0x283 SWBCNT
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0x0000 VSYNC
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0x0001 VBLANK
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0x0002 WSYNC
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0x0003 RSYNC
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0x0004 NUSIZ0
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0x0005 NUSIZ1
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0x0006 COLUP0
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0x0007 COLUP1
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0x0008 COLUPF
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0x0009 COLUBK
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0x000A CTRLPF
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0x000B REFP0
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0x000C REFP1
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0x000D PF0
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0x000E PF1
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0x000F PF2
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0x0010 RESP0
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0x0011 RESP1
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0x0012 RESM0
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0x0013 RESM1
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0x0014 RESBL
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0x0015 AUDC0
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0x0016 AUDC1
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0x0017 AUDF0
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0x0018 AUDF1
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0x0019 AUDV0
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0x001A AUDV1
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0x001B GRP0
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0x001C GRP1
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0x001D ENAM0
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0x001E ENAM1
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0x001F ENABL
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0x0020 HMP0
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0x0021 HMP1
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0x0022 HMM0
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0x0023 HMM1
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0x0024 HMBL
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0x0025 VDELP0
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0x0026 VDELP1
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0x0027 VDELBL
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0x0028 RESMP0
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0x0029 RESMP1
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0x002A HMOVE
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0x002B HMCLR
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0x002C CXCLR
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0x0030 CXM0P
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0x0031 CXM1P
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0x0032 CXP0FB
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0x0033 CXP1FB
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0x0034 CXM0FB
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0x0035 CXM1FB
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0x0036 CXBLPF
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0x0037 CXPPMM
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0x0038 INPT0
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0x0039 INPT1
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0x003A INPT2
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0x003B INPT3
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0x003C INPT4
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0x003D INPT5
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0x0280 SWCHA
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0x0281 SWACNT
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0x0282 SWCHB
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0x0283 SWBCNT
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0x0284 INTIM
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0x0285 TIMINT
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0x0294 TIM1T
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0x0295 TIM8T
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0x0296 TIM64T
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0x0297 T1024T
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0xFFFA NMI_VECTOR
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0xFFFC RESET_VECTOR
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0xFFFE IRQ_VECTOR
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