- [NEW] Simbols de sistema de la Atari 2600 inclosos
- [FIX] opcodes accesibles - [NEW] El desensamblador ja no mostra parts del mapa de memòria que no son RAM o ROM - [FIX] Ja se mostren gràficament tots els branch - [NEW] memdebuginfo de tots els dispositius mapejats disponible
This commit is contained in:
raimon@argo
+370
-366
@@ -3,378 +3,382 @@
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namespace m6502
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{
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enum instruction {
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iADC, iAND, iASL, iBCC, iBCS, iBEQ, iBIT, iBMI, iBNE, iBPL, iBRK, iBVC, iBVS, iCLC,
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iCLD, iCLI, iCLV, iCMP, iCPX, iCPY, iDEC, iDEX, iDEY, iEOR, iINC, iINX, iINY, iJMP,
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iJSR, iLDA, iLDX, iLDY, iLSR, iNOP, iORA, iPHA, iPHP, iPLA, iPLP, iROL, iROR, iRTI,
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iRTS, iSBC, iSEC, iSED, iSEI, iSTA, iSTX, iSTY, iTAX, iTAY, iTSX, iTXA, iTXS, iTYA,
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iILL
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};
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namespace opcodes
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{
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enum instruction {
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iADC, iAND, iASL, iBCC, iBCS, iBEQ, iBIT, iBMI, iBNE, iBPL, iBRK, iBVC, iBVS, iCLC,
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iCLD, iCLI, iCLV, iCMP, iCPX, iCPY, iDEC, iDEX, iDEY, iEOR, iINC, iINX, iINY, iJMP,
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iJSR, iLDA, iLDX, iLDY, iLSR, iNOP, iORA, iPHA, iPHP, iPLA, iPLP, iROL, iROR, iRTI,
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iRTS, iSBC, iSEC, iSED, iSEI, iSTA, iSTX, iSTY, iTAX, iTAY, iTSX, iTXA, iTXS, iTYA,
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iILL
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};
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enum functionalGroup {
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fgLoadStore, fgTransfer, fgStack, fgLogical, fgArithmetic, fgIncDec, fgShift, fgJumpCall, fgBranch, fgStatusFlag, fgSystem, fgIllegal
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};
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enum functionalGroup {
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fgLoadStore, fgTransfer, fgStack, fgLogical, fgArithmetic, fgIncDec, fgShift, fgJumpCall, fgBranch, fgStatusFlag, fgSystem, fgIllegal
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};
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struct instructionProperties {
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const char *name;
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functionalGroup group;
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const char *longName;
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const char *operation;
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const char *description;
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};
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struct instructionProperties {
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const char *name;
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functionalGroup group;
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const char *longName;
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const char *operation;
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const char *description;
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};
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const instructionProperties instructions[] = {
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{"ADC", fgArithmetic, "Add with Carry", "", "This instruction adds the contents of a memory location to the accumulator together with the carry bit. If overflow occurs the carry bit is set, this enables multiple byte addition to be performed." },
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{"AND", fgLogical, "Logical AND", "", "A logical AND is performed, bit by bit, on the accumulator contents using the contents of a byte of memory." },
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{"ASL", fgShift, "Arithmetic Shift Left", "", "This operation shifts all the bits of the accumulator or memory contents one bit left. Bit 0 is set to 0 and bit 7 is placed in the carry flag. The effect of this operation is to multiply the memory contents by 2 (ignoring 2's complement considerations), setting the carry if the result will not fit in 8 bits." },
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{"BCC", fgBranch, "Branch if Carry Clear", "", "If the carry flag is clear then add the relative displacement to the program counter to cause a branch to a new location." },
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{"BCS", fgBranch, "Branch if Carry Set", "", "If the carry flag is set then add the relative displacement to the program counter to cause a branch to a new location." },
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{"BEQ", fgBranch, "Branch if Equal", "", "" },
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{"BIT", fgLogical, "Bit Test", "", "" },
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{"BMI", fgBranch, "Branch if Minus", "", "" },
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{"BNE", fgBranch, "Branch if Not Equal", "", "" },
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{"BPL", fgBranch, "Branch if Positive", "", "" },
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{"BRK", fgSystem, "Force Interrupt", "", "" },
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{"BVC", fgBranch, "Branch if Overflow Clear", "", "" },
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{"BVS", fgBranch, "Branch if Overflow Set", "", "" },
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{"CLC", fgStatusFlag, "Clear Carry Flag", "", "" },
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{"CLD", fgStatusFlag, "Clear Decimal Mode", "", "" },
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{"CLI", fgStatusFlag, "Clear Interrupt Disable", "", "" },
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{"CLV", fgStatusFlag, "Clear Overflow Flag", "", "" },
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{"CMP", fgArithmetic, "Compare", "", "" },
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{"CPX", fgArithmetic, "Compare X Register", "", "" },
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{"CPY", fgArithmetic, "Compare Y Register", "", "" },
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{"DEC", fgIncDec, "Decrement Memory", "", "" },
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{"DEX", fgIncDec, "Decrement X Register", "", "" },
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{"DEY", fgIncDec, "Decrement Y Register", "", "" },
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{"EOR", fgLogical, "Exclusive OR", "", "" },
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{"INC", fgIncDec, "Increment Memory", "", "" },
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{"INX", fgIncDec, "Increment X Register", "", "" },
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{"INY", fgIncDec, "Increment Y Register", "", "" },
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{"JMP", fgJumpCall, "Jump", "", "" },
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{"JSR", fgJumpCall, "Jump to Subroutine", "", "" },
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{"LDA", fgLoadStore, "Load Accumulator", "", "" },
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{"LDX", fgLoadStore, "Load X Register", "", "" },
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{"LDY", fgLoadStore, "Load Y Register", "", "" },
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{"LSR", fgShift, "Logical Shift Right", "", "" },
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{"NOP", fgSystem, "No Operation", "", "" },
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{"ORA", fgLogical, "Logical Incluisve OR", "", "" },
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{"PHA", fgStack, "Push Accumulator", "", "" },
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{"PHP", fgStack, "Push Processor Status", "", "" },
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{"PLA", fgStack, "Pull Accumulator", "", "" },
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{"PLP", fgStack, "Pull Processor Status", "", "" },
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{"ROL", fgShift, "Rotate Left", "", "" },
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{"ROR", fgShift, "Rotate Right", "", "" },
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{"RTI", fgSystem, "Return from Interrupt", "", "" },
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{"RTS", fgJumpCall, "Return from Subroutine", "", "" },
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{"SBC", fgArithmetic, "Substract with Carry", "", "" },
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{"SEC", fgStatusFlag, "Set Carry Flag", "", "" },
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{"SED", fgStatusFlag, "Set Decimal Flag", "", "" },
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{"SEI", fgStatusFlag, "Set Interrupt Disable", "", "" },
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{"STA", fgLoadStore, "Store Accumulator", "", "" },
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{"STX", fgLoadStore, "Store X Register", "", "" },
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{"STY", fgLoadStore, "Store Y Register", "", "" },
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{"TAX", fgTransfer, "Transfer Accumulator to X", "", "" },
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{"TAY", fgTransfer, "Transfer Accumulator to Y", "", "" },
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{"TSX", fgStack, "Transfer Stack Pointer to X", "", "" },
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{"TXA", fgTransfer, "Transfer X to Accumulator", "", "" },
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{"TXS", fgStack, "Transfer X to Stack Pointer", "", "" },
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{"TYA", fgTransfer, "Transfer Y to Accumulator", "", "" },
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{"---", fgIllegal, "Illegal Instruction", "", ""}
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};
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inline const instructionProperties instructions[] = {
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{"ADC", fgArithmetic, "Add with Carry", "", "This instruction adds the contents of a memory location to the accumulator together with the carry bit. If overflow occurs the carry bit is set, this enables multiple byte addition to be performed." },
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{"AND", fgLogical, "Logical AND", "", "A logical AND is performed, bit by bit, on the accumulator contents using the contents of a byte of memory." },
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{"ASL", fgShift, "Arithmetic Shift Left", "", "This operation shifts all the bits of the accumulator or memory contents one bit left. Bit 0 is set to 0 and bit 7 is placed in the carry flag. The effect of this operation is to multiply the memory contents by 2 (ignoring 2's complement considerations), setting the carry if the result will not fit in 8 bits." },
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{"BCC", fgBranch, "Branch if Carry Clear", "", "If the carry flag is clear then add the relative displacement to the program counter to cause a branch to a new location." },
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{"BCS", fgBranch, "Branch if Carry Set", "", "If the carry flag is set then add the relative displacement to the program counter to cause a branch to a new location." },
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{"BEQ", fgBranch, "Branch if Equal", "", "" },
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{"BIT", fgLogical, "Bit Test", "", "" },
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{"BMI", fgBranch, "Branch if Minus", "", "" },
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{"BNE", fgBranch, "Branch if Not Equal", "", "" },
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{"BPL", fgBranch, "Branch if Positive", "", "" },
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{"BRK", fgSystem, "Force Interrupt", "", "" },
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{"BVC", fgBranch, "Branch if Overflow Clear", "", "" },
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{"BVS", fgBranch, "Branch if Overflow Set", "", "" },
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{"CLC", fgStatusFlag, "Clear Carry Flag", "", "" },
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{"CLD", fgStatusFlag, "Clear Decimal Mode", "", "" },
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{"CLI", fgStatusFlag, "Clear Interrupt Disable", "", "" },
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{"CLV", fgStatusFlag, "Clear Overflow Flag", "", "" },
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{"CMP", fgArithmetic, "Compare", "", "" },
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{"CPX", fgArithmetic, "Compare X Register", "", "" },
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{"CPY", fgArithmetic, "Compare Y Register", "", "" },
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{"DEC", fgIncDec, "Decrement Memory", "", "" },
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{"DEX", fgIncDec, "Decrement X Register", "", "" },
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{"DEY", fgIncDec, "Decrement Y Register", "", "" },
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{"EOR", fgLogical, "Exclusive OR", "", "" },
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{"INC", fgIncDec, "Increment Memory", "", "" },
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{"INX", fgIncDec, "Increment X Register", "", "" },
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{"INY", fgIncDec, "Increment Y Register", "", "" },
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{"JMP", fgJumpCall, "Jump", "", "" },
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{"JSR", fgJumpCall, "Jump to Subroutine", "", "" },
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{"LDA", fgLoadStore, "Load Accumulator", "", "" },
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{"LDX", fgLoadStore, "Load X Register", "", "" },
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{"LDY", fgLoadStore, "Load Y Register", "", "" },
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{"LSR", fgShift, "Logical Shift Right", "", "" },
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{"NOP", fgSystem, "No Operation", "", "" },
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{"ORA", fgLogical, "Logical Incluisve OR", "", "" },
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{"PHA", fgStack, "Push Accumulator", "", "" },
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{"PHP", fgStack, "Push Processor Status", "", "" },
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{"PLA", fgStack, "Pull Accumulator", "", "" },
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{"PLP", fgStack, "Pull Processor Status", "", "" },
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{"ROL", fgShift, "Rotate Left", "", "" },
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{"ROR", fgShift, "Rotate Right", "", "" },
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{"RTI", fgSystem, "Return from Interrupt", "", "" },
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{"RTS", fgJumpCall, "Return from Subroutine", "", "" },
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{"SBC", fgArithmetic, "Substract with Carry", "", "" },
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{"SEC", fgStatusFlag, "Set Carry Flag", "", "" },
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{"SED", fgStatusFlag, "Set Decimal Flag", "", "" },
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{"SEI", fgStatusFlag, "Set Interrupt Disable", "", "" },
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{"STA", fgLoadStore, "Store Accumulator", "", "" },
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{"STX", fgLoadStore, "Store X Register", "", "" },
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{"STY", fgLoadStore, "Store Y Register", "", "" },
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{"TAX", fgTransfer, "Transfer Accumulator to X", "", "" },
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{"TAY", fgTransfer, "Transfer Accumulator to Y", "", "" },
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{"TSX", fgStack, "Transfer Stack Pointer to X", "", "" },
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{"TXA", fgTransfer, "Transfer X to Accumulator", "", "" },
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{"TXS", fgStack, "Transfer X to Stack Pointer", "", "" },
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{"TYA", fgTransfer, "Transfer Y to Accumulator", "", "" },
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{"---", fgIllegal, "Illegal Instruction", "", ""}
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};
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enum addressingMode {
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amImplicit, amAccumulator, amImmediate, amZeroPage, amZeroPageX, amZeroPageY,
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amRelative, amAbsolute, amAbsoluteX, amAbsoluteY, amIndirect, amIndirectX, amIndirectY
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};
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struct addressingModeProperties {
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const char *name;
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uint8_t length;
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const char *preText;
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const char *postText;
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};
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enum addressingMode {
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amImplicit, amAccumulator, amImmediate, amZeroPage, amZeroPageX, amZeroPageY,
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amRelative, amAbsolute, amAbsoluteX, amAbsoluteY, amIndirect, amIndirectX, amIndirectY
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};
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struct addressingModeProperties {
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const char *name;
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uint8_t length;
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const char *preText;
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const char *postText;
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};
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const addressingModeProperties addressingModes[] = {
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{"Implicit", 1, "", ""},
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{"Accumulator", 1, "A", ""},
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{"Immediate", 2, "#", ""},
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{"ZeroPage", 2, "", ""},
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{"ZeroPage,X", 2, "", ",X"},
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{"ZeroPage,Y", 2, "", ",Y"},
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{"Relative", 2, "", ""},
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{"Absolute", 3, "", ""},
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{"Absolute,X", 3, "", ",X"},
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{"Absolute,Y", 3, "", ",Y"},
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{"Indirect", 3, "(", ")"},
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{"Indexed Indirect", 2, "(", ",X)"},
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{"Indirect Indexed", 2, "(", "),Y"}
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};
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inline const addressingModeProperties addressingModes[] = {
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{"Implicit", 1, "", ""},
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{"Accumulator", 1, "A", ""},
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{"Immediate", 2, "#", ""},
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{"ZeroPage", 2, "", ""},
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{"ZeroPage,X", 2, "", ",X"},
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{"ZeroPage,Y", 2, "", ",Y"},
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{"Relative", 2, "", ""},
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{"Absolute", 3, "", ""},
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{"Absolute,X", 3, "", ",X"},
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{"Absolute,Y", 3, "", ",Y"},
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{"Indirect", 3, "(", ")"},
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{"Indexed Indirect", 2, "(", ",X)"},
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{"Indirect Indexed", 2, "(", "),Y"}
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};
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struct opcodeProperties {
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instruction instr;
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addressingMode addrMode;
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uint8_t cycles;
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bool ifBoundaryCrossed;
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bool ifBranchTaken;
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};
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struct opcodeProperties {
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instruction instr;
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addressingMode addrMode;
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uint8_t cycles;
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bool ifBoundaryCrossed;
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bool ifBranchTaken;
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};
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const opcodeProperties opcodeDescriptors[256] = {
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{iBRK, amImplicit, 7, false, false},
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{iORA, amIndirectX, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iORA, amZeroPage, 3, false, false},
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{iASL, amZeroPage, 5, false, false},
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{iILL, amImplicit, 2, false, false},
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{iPHP, amImplicit, 3, false, false},
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{iORA, amImmediate, 2, false, false},
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{iASL, amAccumulator, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iORA, amAbsolute, 4, false, false},
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{iASL, amAbsolute, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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{iBPL, amRelative, 2, true, true },
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{iORA, amIndirectY, 5, true, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iORA, amZeroPageX, 4, false, false},
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{iASL, amZeroPageX, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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{iCLC, amImplicit, 2, false, false},
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{iORA, amAbsoluteY, 4, true, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iORA, amAbsoluteX, 4, true, false},
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{iASL, amAbsoluteX, 7, false, false},
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{iILL, amImplicit, 2, false, false},
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{iJSR, amAbsolute, 6, false, false},
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{iAND, amIndirectX, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iBIT, amZeroPage, 3, false, false},
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{iAND, amZeroPage, 3, false, false},
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{iROL, amZeroPage, 5, false, false},
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{iILL, amImplicit, 2, false, false},
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{iPLP, amImplicit, 4, false, false},
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{iAND, amImmediate, 2, false, false},
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{iROL, amAccumulator, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iBIT, amAbsolute, 4, false, false},
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{iAND, amAbsolute, 4, false, false},
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{iROL, amAbsolute, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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{iBMI, amRelative, 2, true, true },
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{iAND, amIndirectY, 5, true, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iAND, amZeroPageX, 4, false, false},
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{iROL, amZeroPageX, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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{iSEC, amImplicit, 2, false, false},
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{iAND, amAbsoluteY, 4, true, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iAND, amAbsoluteX, 4, true, false},
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{iROL, amAbsoluteX, 7, false, false},
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{iILL, amImplicit, 2, false, false},
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{iRTI, amImplicit, 6, false, false},
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{iEOR, amIndirectX, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iEOR, amZeroPage, 3, false, false},
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{iLSR, amZeroPage, 5, false, false},
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{iILL, amImplicit, 2, false, false},
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{iPHA, amImplicit, 3, false, false},
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{iEOR, amImmediate, 2, false, false},
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{iLSR, amAccumulator, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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||||
{iJMP, amAbsolute, 3, false, false},
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||||
{iEOR, amAbsolute, 4, false, false},
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{iLSR, amAbsolute, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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{iBVC, amRelative, 2, true, true },
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{iEOR, amIndirectY, 5, true, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iEOR, amZeroPageX, 4, false, false},
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{iLSR, amZeroPageX, 6, false, false},
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{iILL, amImplicit, 2, false, false},
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{iCLI, amImplicit, 2, false, false},
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{iEOR, amAbsoluteY, 4, true, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iILL, amImplicit, 2, false, false},
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{iEOR, amAbsoluteX, 4, true, false},
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{iLSR, amAbsoluteX, 7, false, false},
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{iILL, amImplicit, 2, false, false},
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{iRTS, amImplicit, 6, false, false},
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{iADC, amIndirectX, 6, false, false},
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{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
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||||
{iILL, amImplicit, 2, false, false},
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||||
{iADC, amZeroPage, 3, false, false},
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{iROR, amZeroPage, 5, false, false},
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{iILL, amImplicit, 2, false, false},
|
||||
{iPLA, amImplicit, 4, false, false},
|
||||
{iADC, amImmediate, 2, false, false},
|
||||
{iROR, amAccumulator, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iJMP, amIndirect, 5, false, false},
|
||||
{iADC, amAbsolute, 4, false, false},
|
||||
{iROR, amAbsolute, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBVS, amRelative, 2, true, true },
|
||||
{iADC, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iADC, amZeroPageX, 4, false, false},
|
||||
{iROR, amZeroPageX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSEI, amImplicit, 2, false, false},
|
||||
{iADC, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iADC, amAbsoluteX, 4, true, false},
|
||||
{iROR, amAbsoluteX, 7, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTA, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTY, amZeroPage, 3, false, false},
|
||||
{iSTA, amZeroPage, 3, false, false},
|
||||
{iSTX, amZeroPage, 3, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iDEY, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iTXA, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTY, amAbsolute, 4, false, false},
|
||||
{iSTA, amAbsolute, 4, false, false},
|
||||
{iSTX, amAbsolute, 4, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBCC, amRelative, 2, true, true },
|
||||
{iSTA, amIndirectY, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTY, amZeroPageX, 4, false, false},
|
||||
{iSTA, amZeroPageX, 4, false, false},
|
||||
{iSTX, amZeroPageY, 4, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iTYA, amImplicit, 2, false, false},
|
||||
{iSTA, amAbsoluteY, 5, false, false},
|
||||
{iTXS, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTA, amAbsoluteX, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amImmediate, 2, false, false},
|
||||
{iLDA, amIndirectX, 6, false, false},
|
||||
{iLDX, amImmediate, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amZeroPage, 3, false, false},
|
||||
{iLDA, amZeroPage, 3, false, false},
|
||||
{iLDX, amZeroPage, 3, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iTAY, amImplicit, 2, false, false},
|
||||
{iLDA, amImmediate, 2, false, false},
|
||||
{iTAX, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amAbsolute, 4, false, false},
|
||||
{iLDA, amAbsolute, 4, false, false},
|
||||
{iLDX, amAbsolute, 4, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBCS, amRelative, 2, true, true },
|
||||
{iLDA, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amZeroPageX, 4, false, false},
|
||||
{iLDA, amZeroPageX, 4, false, false},
|
||||
{iLDX, amZeroPageY, 4, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCLV, amImplicit, 2, false, false},
|
||||
{iLDA, amAbsoluteY, 4, true, false},
|
||||
{iTSX, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amAbsoluteX, 4, true, false},
|
||||
{iLDA, amAbsoluteX, 4, true, false},
|
||||
{iLDX, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPY, amImmediate, 2, false, false},
|
||||
{iCMP, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPY, amZeroPage, 3, false, false},
|
||||
{iCMP, amZeroPage, 3, false, false},
|
||||
{iDEC, amZeroPage, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iINY, amImplicit, 2, false, false},
|
||||
{iCMP, amImmediate, 2, false, false},
|
||||
{iDEX, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPY, amAbsolute, 4, false, false},
|
||||
{iCMP, amAbsolute, 4, false, false},
|
||||
{iDEC, amAbsolute, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBNE, amRelative, 2, true, true },
|
||||
{iCMP, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCMP, amZeroPageX, 4, false, false},
|
||||
{iDEC, amZeroPageX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCLD, amImplicit, 2, false, false},
|
||||
{iCMP, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCMP, amAbsoluteX, 4, true, false},
|
||||
{iDEC, amAbsoluteX, 7, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPX, amImmediate, 2, false, false},
|
||||
{iSBC, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPX, amZeroPage, 3, false, false},
|
||||
{iSBC, amZeroPage, 3, false, false},
|
||||
{iINC, amZeroPage, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iINX, amImplicit, 2, false, false},
|
||||
{iSBC, amImmediate, 2, false, false},
|
||||
{iNOP, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPX, amAbsolute, 4, false, false},
|
||||
{iSBC, amAbsolute, 4, false, false},
|
||||
{iINC, amAbsolute, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBEQ, amRelative, 2, true, true },
|
||||
{iSBC, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSBC, amZeroPageX, 4, false, false},
|
||||
{iINC, amZeroPageX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSED, amImplicit, 2, false, false},
|
||||
{iSBC, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSBC, amAbsoluteX, 4, true, false},
|
||||
{iINC, amAbsoluteX, 7, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
};
|
||||
inline const opcodeProperties opcodeDescriptors[256] = {
|
||||
{iBRK, amImplicit, 7, false, false},
|
||||
{iORA, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iORA, amZeroPage, 3, false, false},
|
||||
{iASL, amZeroPage, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iPHP, amImplicit, 3, false, false},
|
||||
{iORA, amImmediate, 2, false, false},
|
||||
{iASL, amAccumulator, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iORA, amAbsolute, 4, false, false},
|
||||
{iASL, amAbsolute, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBPL, amRelative, 2, true, true },
|
||||
{iORA, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iORA, amZeroPageX, 4, false, false},
|
||||
{iASL, amZeroPageX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCLC, amImplicit, 2, false, false},
|
||||
{iORA, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iORA, amAbsoluteX, 4, true, false},
|
||||
{iASL, amAbsoluteX, 7, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iJSR, amAbsolute, 6, false, false},
|
||||
{iAND, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBIT, amZeroPage, 3, false, false},
|
||||
{iAND, amZeroPage, 3, false, false},
|
||||
{iROL, amZeroPage, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iPLP, amImplicit, 4, false, false},
|
||||
{iAND, amImmediate, 2, false, false},
|
||||
{iROL, amAccumulator, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBIT, amAbsolute, 4, false, false},
|
||||
{iAND, amAbsolute, 4, false, false},
|
||||
{iROL, amAbsolute, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBMI, amRelative, 2, true, true },
|
||||
{iAND, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iAND, amZeroPageX, 4, false, false},
|
||||
{iROL, amZeroPageX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSEC, amImplicit, 2, false, false},
|
||||
{iAND, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iAND, amAbsoluteX, 4, true, false},
|
||||
{iROL, amAbsoluteX, 7, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iRTI, amImplicit, 6, false, false},
|
||||
{iEOR, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iEOR, amZeroPage, 3, false, false},
|
||||
{iLSR, amZeroPage, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iPHA, amImplicit, 3, false, false},
|
||||
{iEOR, amImmediate, 2, false, false},
|
||||
{iLSR, amAccumulator, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iJMP, amAbsolute, 3, false, false},
|
||||
{iEOR, amAbsolute, 4, false, false},
|
||||
{iLSR, amAbsolute, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBVC, amRelative, 2, true, true },
|
||||
{iEOR, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iEOR, amZeroPageX, 4, false, false},
|
||||
{iLSR, amZeroPageX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCLI, amImplicit, 2, false, false},
|
||||
{iEOR, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iEOR, amAbsoluteX, 4, true, false},
|
||||
{iLSR, amAbsoluteX, 7, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iRTS, amImplicit, 6, false, false},
|
||||
{iADC, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iADC, amZeroPage, 3, false, false},
|
||||
{iROR, amZeroPage, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iPLA, amImplicit, 4, false, false},
|
||||
{iADC, amImmediate, 2, false, false},
|
||||
{iROR, amAccumulator, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iJMP, amIndirect, 5, false, false},
|
||||
{iADC, amAbsolute, 4, false, false},
|
||||
{iROR, amAbsolute, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBVS, amRelative, 2, true, true },
|
||||
{iADC, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iADC, amZeroPageX, 4, false, false},
|
||||
{iROR, amZeroPageX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSEI, amImplicit, 2, false, false},
|
||||
{iADC, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iADC, amAbsoluteX, 4, true, false},
|
||||
{iROR, amAbsoluteX, 7, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTA, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTY, amZeroPage, 3, false, false},
|
||||
{iSTA, amZeroPage, 3, false, false},
|
||||
{iSTX, amZeroPage, 3, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iDEY, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iTXA, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTY, amAbsolute, 4, false, false},
|
||||
{iSTA, amAbsolute, 4, false, false},
|
||||
{iSTX, amAbsolute, 4, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBCC, amRelative, 2, true, true },
|
||||
{iSTA, amIndirectY, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTY, amZeroPageX, 4, false, false},
|
||||
{iSTA, amZeroPageX, 4, false, false},
|
||||
{iSTX, amZeroPageY, 4, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iTYA, amImplicit, 2, false, false},
|
||||
{iSTA, amAbsoluteY, 5, false, false},
|
||||
{iTXS, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSTA, amAbsoluteX, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amImmediate, 2, false, false},
|
||||
{iLDA, amIndirectX, 6, false, false},
|
||||
{iLDX, amImmediate, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amZeroPage, 3, false, false},
|
||||
{iLDA, amZeroPage, 3, false, false},
|
||||
{iLDX, amZeroPage, 3, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iTAY, amImplicit, 2, false, false},
|
||||
{iLDA, amImmediate, 2, false, false},
|
||||
{iTAX, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amAbsolute, 4, false, false},
|
||||
{iLDA, amAbsolute, 4, false, false},
|
||||
{iLDX, amAbsolute, 4, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBCS, amRelative, 2, true, true },
|
||||
{iLDA, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amZeroPageX, 4, false, false},
|
||||
{iLDA, amZeroPageX, 4, false, false},
|
||||
{iLDX, amZeroPageY, 4, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCLV, amImplicit, 2, false, false},
|
||||
{iLDA, amAbsoluteY, 4, true, false},
|
||||
{iTSX, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iLDY, amAbsoluteX, 4, true, false},
|
||||
{iLDA, amAbsoluteX, 4, true, false},
|
||||
{iLDX, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPY, amImmediate, 2, false, false},
|
||||
{iCMP, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPY, amZeroPage, 3, false, false},
|
||||
{iCMP, amZeroPage, 3, false, false},
|
||||
{iDEC, amZeroPage, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iINY, amImplicit, 2, false, false},
|
||||
{iCMP, amImmediate, 2, false, false},
|
||||
{iDEX, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPY, amAbsolute, 4, false, false},
|
||||
{iCMP, amAbsolute, 4, false, false},
|
||||
{iDEC, amAbsolute, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBNE, amRelative, 2, true, true },
|
||||
{iCMP, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCMP, amZeroPageX, 4, false, false},
|
||||
{iDEC, amZeroPageX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCLD, amImplicit, 2, false, false},
|
||||
{iCMP, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCMP, amAbsoluteX, 4, true, false},
|
||||
{iDEC, amAbsoluteX, 7, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPX, amImmediate, 2, false, false},
|
||||
{iSBC, amIndirectX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPX, amZeroPage, 3, false, false},
|
||||
{iSBC, amZeroPage, 3, false, false},
|
||||
{iINC, amZeroPage, 5, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iINX, amImplicit, 2, false, false},
|
||||
{iSBC, amImmediate, 2, false, false},
|
||||
{iNOP, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iCPX, amAbsolute, 4, false, false},
|
||||
{iSBC, amAbsolute, 4, false, false},
|
||||
{iINC, amAbsolute, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iBEQ, amRelative, 2, true, true },
|
||||
{iSBC, amIndirectY, 5, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSBC, amZeroPageX, 4, false, false},
|
||||
{iINC, amZeroPageX, 6, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSED, amImplicit, 2, false, false},
|
||||
{iSBC, amAbsoluteY, 4, true, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
{iSBC, amAbsoluteX, 4, true, false},
|
||||
{iINC, amAbsoluteX, 7, false, false},
|
||||
{iILL, amImplicit, 2, false, false},
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
+24
-4
@@ -5,6 +5,7 @@
|
||||
#include "mem.h"
|
||||
#include "6502m.h"
|
||||
#include "6502dis.h"
|
||||
#include "6502_opcodes.h"
|
||||
#include "display.h"
|
||||
#include "ui.h"
|
||||
#include "ui_window.h"
|
||||
@@ -435,6 +436,8 @@ namespace m6502debugger
|
||||
|
||||
void printDissasemblerLine(const uint16_t address, const int line, const bool heuristics=false)
|
||||
{
|
||||
const bool isMemory = mem::debug::getInfo(address).memType & mdtMemory;
|
||||
|
||||
uint8_t colors[4] = { COLOR_RED, COLOR_CYAN, COLOR_WHITE, COLOR_WHITE};
|
||||
const uint8_t tag = tags[address];
|
||||
if ( !(tag & (MEMTAG_TINST | MEMTAG_TREPEAT)) ) colors[3]=COLOR_GRAY;
|
||||
@@ -448,6 +451,8 @@ namespace m6502debugger
|
||||
if (breakpoints[address]&9) ui::printtxt(0,line,"*", colors[0]);
|
||||
ui::printtxt(1,line,tohex(address,4), colors[1]);
|
||||
|
||||
if (!isMemory) return;
|
||||
|
||||
if ( (tag & MEMTAG_INST) || heuristics ) {
|
||||
const char *sym = m6502dis::getSymbol(address);
|
||||
if (sym[0]!=0) ui::printtxt(7,line, sym, COLOR_YELLOW);
|
||||
@@ -493,20 +498,21 @@ namespace m6502debugger
|
||||
printDissasemblerLine(pc, (num_lines/2)-1, true);
|
||||
|
||||
for (int i=num_lines/2;i<num_lines;++i) {
|
||||
pos += m6502dis::getOpcodeSize(pos);
|
||||
pos += mem::debug::getInfo(pos).memType&mdtMemory ? m6502dis::getOpcodeSize(pos) : 1;
|
||||
line_address[i] = pos;
|
||||
printDissasemblerLine(pos, i, true);
|
||||
}
|
||||
|
||||
pos = pc;
|
||||
for (int i=(num_lines/2)-2;i>=0;--i) {
|
||||
pos = find_previous_opcode(pos);
|
||||
pos = mem::debug::getInfo(pos).memType&mdtMemory ? find_previous_opcode(pos) : 1;
|
||||
line_address[i] = pos;
|
||||
printDissasemblerLine(pos, i, true);
|
||||
}
|
||||
|
||||
for (int i=0;i<num_lines;++i) {
|
||||
if (mem::read(line_address[i])==0xd0) {
|
||||
if (m6502::opcodes::instructions[m6502::opcodes::opcodeDescriptors[mem::read(line_address[i])].instr].group == m6502::opcodes::fgBranch) {
|
||||
// if (mem::read(line_address[i])==0xd0) {
|
||||
int8_t offset = mem::read(line_address[i]+1);
|
||||
uint16_t target_address = line_address[i] + 2 + offset;
|
||||
if (offset<0) {
|
||||
@@ -526,7 +532,21 @@ namespace m6502debugger
|
||||
ui::printvline(17,i,-1,COLOR_RED);
|
||||
}
|
||||
} else {
|
||||
|
||||
int j = i;
|
||||
while (j<num_lines){
|
||||
if (line_address[j] == target_address) {
|
||||
ui::printhline(17,i,18,COLOR_RED);
|
||||
ui::printhline(17,j,18,COLOR_RED);
|
||||
ui::printvline(17,i,j,COLOR_RED);
|
||||
break;
|
||||
}
|
||||
j++;
|
||||
}
|
||||
if (j==num_lines) {
|
||||
ui::printhline(17,i,18,COLOR_RED);
|
||||
//ui::printhline(17,0,18,COLOR_RED);
|
||||
ui::printvline(17,i,num_lines,COLOR_RED);
|
||||
}
|
||||
}
|
||||
//ui::printtxt(6,i,tohex(target_address,4),COLOR_BLACK);
|
||||
}
|
||||
|
||||
@@ -1,6 +1,15 @@
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
|
||||
enum mappedDeviceType {
|
||||
mdtMemory = 1,
|
||||
mdtRead = 2,
|
||||
mdtWrite = 4,
|
||||
mdtROM = 3,
|
||||
mdtRAM = 7,
|
||||
mdtRegister = 8
|
||||
};
|
||||
|
||||
struct memDebugInfo {
|
||||
const char* name;
|
||||
uint8_t memType;
|
||||
|
||||
+5
-1
@@ -127,7 +127,11 @@ namespace pia
|
||||
{
|
||||
const memDebugInfo getInfo(uint16_t address)
|
||||
{
|
||||
|
||||
if (address & 0x200) {
|
||||
return {"PIA", mdtRegister, address};
|
||||
} else {
|
||||
return {"RAM", mdtRAM, address & 0xff};
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -37,4 +37,11 @@ namespace rom
|
||||
data[address & mask] = value;
|
||||
}
|
||||
|
||||
namespace debug
|
||||
{
|
||||
const memDebugInfo getInfo(uint16_t address)
|
||||
{
|
||||
return {"ROM", mdtROM, 0x1000 | (address & mask)};
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -461,4 +461,12 @@ namespace tia
|
||||
return rdy_low;
|
||||
}
|
||||
|
||||
namespace debug
|
||||
{
|
||||
const memDebugInfo getInfo(uint16_t address)
|
||||
{
|
||||
return {"TIA", mdtRegister, address};
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
+72
-1
@@ -1 +1,72 @@
|
||||
0x283 SWBCNT
|
||||
0x0000 VSYNC
|
||||
0x0001 VBLANK
|
||||
0x0002 WSYNC
|
||||
0x0003 RSYNC
|
||||
0x0004 NUSIZ0
|
||||
0x0005 NUSIZ1
|
||||
0x0006 COLUP0
|
||||
0x0007 COLUP1
|
||||
0x0008 COLUPF
|
||||
0x0009 COLUBK
|
||||
0x000A CTRLPF
|
||||
0x000B REFP0
|
||||
0x000C REFP1
|
||||
0x000D PF0
|
||||
0x000E PF1
|
||||
0x000F PF2
|
||||
0x0010 RESP0
|
||||
0x0011 RESP1
|
||||
0x0012 RESM0
|
||||
0x0013 RESM1
|
||||
0x0014 RESBL
|
||||
0x0015 AUDC0
|
||||
0x0016 AUDC1
|
||||
0x0017 AUDF0
|
||||
0x0018 AUDF1
|
||||
0x0019 AUDV0
|
||||
0x001A AUDV1
|
||||
0x001B GRP0
|
||||
0x001C GRP1
|
||||
0x001D ENAM0
|
||||
0x001E ENAM1
|
||||
0x001F ENABL
|
||||
0x0020 HMP0
|
||||
0x0021 HMP1
|
||||
0x0022 HMM0
|
||||
0x0023 HMM1
|
||||
0x0024 HMBL
|
||||
0x0025 VDELP0
|
||||
0x0026 VDELP1
|
||||
0x0027 VDELBL
|
||||
0x0028 RESMP0
|
||||
0x0029 RESMP1
|
||||
0x002A HMOVE
|
||||
0x002B HMCLR
|
||||
0x002C CXCLR
|
||||
0x0030 CXM0P
|
||||
0x0031 CXM1P
|
||||
0x0032 CXP0FB
|
||||
0x0033 CXP1FB
|
||||
0x0034 CXM0FB
|
||||
0x0035 CXM1FB
|
||||
0x0036 CXBLPF
|
||||
0x0037 CXPPMM
|
||||
0x0038 INPT0
|
||||
0x0039 INPT1
|
||||
0x003A INPT2
|
||||
0x003B INPT3
|
||||
0x003C INPT4
|
||||
0x003D INPT5
|
||||
0x0280 SWCHA
|
||||
0x0281 SWACNT
|
||||
0x0282 SWCHB
|
||||
0x0283 SWBCNT
|
||||
0x0284 INTIM
|
||||
0x0285 TIMINT
|
||||
0x0294 TIM1T
|
||||
0x0295 TIM8T
|
||||
0x0296 TIM64T
|
||||
0x0297 T1024T
|
||||
0xFFFA NMI_VECTOR
|
||||
0xFFFC RESET_VECTOR
|
||||
0xFFFE IRQ_VECTOR
|
||||
|
||||
Reference in New Issue
Block a user