- Seguim
This commit is contained in:
118
6502m.cpp
118
6502m.cpp
@@ -11,17 +11,6 @@
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#define fV 0b01000000 // Overflow
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#define fN 0b10000000 // Negative
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// Jump types
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#define cUnconditional 255
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#define cNZ 0
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#define cZ 1
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#define cNC 2
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#define cC 3
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#define cNN 4
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#define cN 5
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#define cNV 6
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#define cV 7
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// Addressing modes
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#define aAccumulator 0
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#define aImmediate 1
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@@ -103,6 +92,10 @@ namespace m6502
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miReadAddress,
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miReadAddressAndSkip,
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miWriteRegister,
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miWriteAddress,
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miPushA,
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miFetchOperandAndCheckBranch,
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miCheckIfPageCrossed,
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miNumMicroinstructions
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};
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@@ -114,6 +107,68 @@ namespace m6502
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/* 0x03 --- */ { miFetchOpcode },
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/* 0x04 --- */ { miFetchOpcode },
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/* 0x05 ORA zpg */ { miFetchOperandLo, miReadAddress, miFetchOpcode },
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/* 0x06 ASL zpg */ { miFetchOperandLo, miReadAddress, miWriteAddress, miWriteAddress, miFetchOpcode },
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/* 0x07 --- */ { miFetchOpcode },
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/* 0x08 PHP */ { miFetchOperandLo, miPushP, miFetchOpcode },
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/* 0x09 ORA imm */ { miFetchOperandLo, miFetchOpcode },
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/* 0x0A ASL A */ { miFakeFetchOperand, miFetchOpcode },
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/* 0x0B --- */ { miFetchOpcode },
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/* 0x0C --- */ { miFetchOpcode },
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/* 0x0D ORA abs */ { miFetchOperandLo, miFetchOperandHi, miReadAddress, miFetchOpcode },
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/* 0x0E ASL abs */ { miFetchOperandLo, miFetchOperandHi, miReadAddress, miWriteAddress, miWriteAddress, miFetchOpcode },
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/* 0x0F --- */ { miFetchOpcode },
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/* 0x10 BPL */ { miFetchOperandAndCheckBranch, miCheckIfPageCrossed, miFakeFetchOperand, miFetchOpcode },
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/* 0x11 ORA ind,Y */ { miFetchOperandLo, miFetchAddressLo, miFetchAddressHiAndIndex, miReadAddressAndSkip, miReadAddress, miFetchOpcode },
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/* 0x12 --- */ { miFetchOpcode },
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/* 0x13 --- */ { miFetchOpcode },
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/* 0x14 --- */ { miFetchOpcode },
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/* 0x15 ORA zpg,X */ { miFetchOperandLo, miIndexX, miReadAddress, miFetchOpcode },
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/* 0x16 ASL zpg,X */ { miFetchOperandLo, miIndexX, miReadAddress, miWriteAddress, miWriteAddress, miFetchOpcode },
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/* 0x17 --- */ { miFetchOpcode },
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/* 0x18 CLC */ { miFetchOperandLo, miFetchOpcode },
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/* 0x19 ORA abs,Y */ { miFetchOperandLo, miFetchOperandHiAndIndexY, miReadAddressAndSkip, miReadAddress, miFetchOpcode },
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/* 0x1A --- */ { miFetchOpcode },
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/* 0x1B --- */ { miFetchOpcode },
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/* 0x1C --- */ { miFetchOpcode },
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/* 0x1D ORA abs,X */ { miFetchOperandLo, miFetchOperandHiAndIndexX, miReadAddressAndSkip, miReadAddress, miFetchOpcode },
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/* 0x1E ASL abs,X */ { miFetchOperandLo, miFetchOperandHiAndIndexX, miReadAddress, miReadAddress, miWriteAddress, miWriteAddress, miFetchOpcode },
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/* 0x1F --- */ { miFetchOpcode },
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/* 0x20 JSR abs */ { },
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/* 0x21 ORA X,ind */ { miFetchOperandLo, miIndexX, miFetchAddressLo, miFetchAddressHi, miReadAddress, miFetchOpcode },
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/* 0x22 --- */ { miFetchOpcode },
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/* 0x23 --- */ { miFetchOpcode },
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/* 0x24 --- */ { miFetchOpcode },
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/* 0x25 ORA zpg */ { miFetchOperandLo, miReadAddress, miFetchOpcode },
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/* 0x26 ASL zpg */ { miFetchOperandLo, miReadAddress, miWriteAddress, miWriteAddress, miFetchOpcode },
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/* 0x27 --- */ { miFetchOpcode },
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/* 0x28 PHP */ { miFetchOperandLo, miPushP, miFetchOpcode },
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/* 0x29 ORA imm */ { miFetchOperandLo, miFetchOpcode },
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/* 0x2A ASL A */ { miFakeFetchOperand, miFetchOpcode },
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/* 0x2B --- */ { miFetchOpcode },
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/* 0x2C --- */ { miFetchOpcode },
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/* 0x2D ORA abs */ { miFetchOperandLo, miFetchOperandHi, miReadAddress, miFetchOpcode },
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/* 0x2E ASL abs */ { miFetchOperandLo, miFetchOperandHi, miReadAddress, miWriteAddress, miWriteAddress, miFetchOpcode },
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/* 0x2F --- */ { miFetchOpcode },
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/* 0x30 BPL */ { miFetchOperandAndCheckBranch, miCheckIfPageCrossed, miFakeFetchOperand, miFetchOpcode },
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/* 0x31 ORA ind,Y */ { miFetchOperandLo, miFetchAddressLo, miFetchAddressHiAndIndex, miReadAddressAndSkip, miReadAddress, miFetchOpcode },
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/* 0x32 --- */ { miFetchOpcode },
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/* 0x33 --- */ { miFetchOpcode },
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/* 0x34 --- */ { miFetchOpcode },
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/* 0x35 ORA zpg,X */ { miFetchOperandLo, miIndexX, miReadAddress, miFetchOpcode },
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/* 0x36 ASL zpg,X */ { miFetchOperandLo, miIndexX, miReadAddress, miWriteAddress, miWriteAddress, miFetchOpcode },
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/* 0x37 --- */ { miFetchOpcode },
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/* 0x38 CLC */ { miFetchOperandLo, miFetchOpcode },
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/* 0x39 ORA abs,Y */ { miFetchOperandLo, miFetchOperandHiAndIndexY, miReadAddressAndSkip, miReadAddress, miFetchOpcode },
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/* 0x3A --- */ { miFetchOpcode },
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/* 0x3B --- */ { miFetchOpcode },
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/* 0x3C --- */ { miFetchOpcode },
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/* 0x3D ORA abs,X */ { miFetchOperandLo, miFetchOperandHiAndIndexX, miReadAddressAndSkip, miReadAddress, miFetchOpcode },
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/* 0x3E ASL abs,X */ { miFetchOperandLo, miFetchOperandHiAndIndexX, miReadAddress, miReadAddress, miWriteAddress, miWriteAddress, miFetchOpcode },
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/* 0x3F --- */ { miFetchOpcode },
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};
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void SetFlags(uint8_t flags)
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@@ -127,6 +182,19 @@ namespace m6502
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void DoOpcodeWork()
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{
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switch (rI&0x03) {
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case 0: /* Clear/set flags*/
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if ( (rI&0x1c)==0x18 ) {
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switch (rI>>5) {
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case 0: rP &= ~fC; break;
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case 1: rP |= fC; break;
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case 2: rP &= ~fI; break;
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case 3: rP |= fI; break;
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case 5: rP &= ~fV; break;
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case 6: rP &= ~fD; break;
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case 7: rP |= fD; break;
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}
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}
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break;
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case 1: /* ALU */
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switch ((rI>>5)&0x07) {
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case 0: /* ORA */ rB = rA | rB; SetFlags(fN|fZ); rA = rB; break;
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@@ -141,6 +209,27 @@ namespace m6502
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};
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}
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void DoRMW()
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{
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switch (rI&0x03) {
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case 2: /* RMW */
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if ((rI & 0xF)==0xA) rB = rA;
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switch ((rI>>5)&0x07) {
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case 0: /* ASL */ rP = ( rP & ~fC ) | ( (rB & 0x80)>>7 ); rB = rB << 1; SetFlags(fN|fZ); break;
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};
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if ((rI & 0xF)==0xA) rA = rB;
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break;
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};
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}
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bool BranchCondition()
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{
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const uint8_t flags[4] = {fN, fV, fC, fZ};
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const uint8_t flag = flags[rI>>6];
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const bool condition = (rI>>5)&1;
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return (rP & flag) == condition;
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}
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void InsertFetchOpcode()
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{
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microcode[microcode_pos] = miFetchOpcode;
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@@ -174,12 +263,17 @@ namespace m6502
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void ReadAddressAndSkip() { rB = mem::read(rAD); rAD_hi += rTEMP_hi; if (rTEMP_hi) InsertFetchOpcode(); }
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void WriteRegister() { mem::write(rAD, (rI&3)==1 ? rA : (rI&3)==2 ? rX : rY ); }
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void WriteAddress() { mem::write(rAD, rB); DoRMW(); }
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void PushA() { mem::write(0x0100+(rS++), rA); }
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void FetchOperandAndCheckBranch() { FetchOperandLo(); if (!BranchCondition()) InsertFetchOpcode(); else { rT = rPC_hi; rPC = rPC + (int8_t)rB; } }
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void CheckIfPageCrossed() { FakeFetchOperand(); if (rPC_hi == rT) InsertFetchOpcode(); }
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void (*microinstructions[miNumMicroinstructions])(void) {
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FetchOpcode, FakeFetchOperand, FetchOperandLo, FetchOperandHi, FetchOperandHiAndIndexX, FetchOperandHiAndIndexY,
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PushPCHi, PushPCLo, PushP, PCLoInt, PCHiInt,
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IndexX, FetchAddressLo, FetchAddressHi, FetchAddressHiAndIndex, ReadAddress,
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ReadAddressAndSkip, WriteRegister };
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ReadAddressAndSkip, WriteRegister, WriteAddress, PushA, FetchOperandAndCheckBranch,
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CheckIfPageCrossed };
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void reset()
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{
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@@ -202,8 +202,8 @@ WriteAddress
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Mem::Write(Address, B);
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DoOpcodeWork();
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CheckIfTaken
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FakeFetchOperand();
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FetchOperandAndCheckBranch
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Address.Lo = B = Mem::Read(PC++);
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If (!condition)
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InsertFetchOpcode();
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else
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